Hewlett-Packard, these days better known for printers than innovation, has announced a breakthrough in chip manufacturing. The new process allows for eight times more gates to be put on each chip while simultaneously cutting power consumption. The nanotechnology also allows for higher fault tolerance and even possible reprogramming of chips even after the parts are installed in consumer electronics.

HP Labs researchers, Greg Snider and Stan Williams, published the news in published in Nanotechnology, a journal of the British Institute of Physics.

The advance allows more field programmable gate arrays (FPGAs) to be packed into a chip. FPGAs are similar to regular logic gates except they can also handle more complex operations. For those of you that didn’t have a computer architecture class, logic gates are the basic building blocks of a computer’s processor. The logic gates manipulate the ones and zero’s of binary to implement basic computer logic.

The breakthrough has come at a time when many experts have predicted the end of Moore’s Law and the possible results for the computer industry. According to Williams, an HP Senior Fellow and director, Quantum Science Research, HP Labs, “As conventional chip electronics continue to shrink, Moore’s Law is on a collision course with the laws of physics. Excessive heating and defective device operation arise at the nanoscale. What we’ve been able to do is combine conventional CMOS technology with nanoscale switching devices in a hybrid circuit to increase effective transistor density, reduce power dissipation, and dramatically improve tolerance to defective devices.”

Another feature of the chips is that they will function effectively even with 20% of the connections randomly broken. This is important in chip manufacturing as increasing demands for high tolerances are making chip production more expensive. According to Snider, senior architect, Quantum Science Research, HP Labs, “The expense of fabricating chips is increasing dramatically with the demands of increasing manufacturing tolerances. We believe this approach could increase the usable device density of FPGAs by a factor of eight, using tolerances that are no greater than those required of today’s devices.”